1. Field of the Invention
The present invention relates generally to transmission systems and methods and, more particularly, to a system and method for physical layer device enabled clock diagnostics.
2. Introduction
Ethernet-based systems rely on a fundamental clock to transmit data. For example, for gigabit Ethernet such as 1000BASE-T this fundamental clock is a 125 MHz clock. In modern multi-port systems, all of the clocks are typically derived from a single oscillator. The receive clock, for example, often represents a phase adjusted version of the transmit clock.
More specifically, the 1000BASE-T system allows for one link partner to be configured as a master device and the other link partner to be configured as a slave device. In this master-slave configuration, the slave device is designed to transmit its data at the exact same rate at which the master device is transmitting its data. As noted above, 1000BASE-T transmission has the master device transmitting based on a 125 MHz clock. In reality, however, the clocks for the master device and the slave device will vary by some small amount due to variations (ε) in the crystal oscillator when considering factors such as process and temperature variations.
To enable transmission at the same rate as the master device, it is therefore a function of the slave device to determine the value of ε from the incoming received signal and to ensure that it transmits to the master device at 125 MHz+ε.
Timing recovery elements within the slave device enable a determination of the value of ε. When the timing recovery process involves the received symbols it is referred to as decision directed (DD) timing recovery, otherwise it is referred to as non-decision directed (NDD) timing recovery. Regardless of the particular timing recovery system and/or method used, its proper functioning is a key element in ensuring that the master and slave devices communicate with low packet and symbol error rates. What is needed therefore is a mechanism that enables the PHY to ensure that the clock generation mechanism is operating correctly in generating a clock usable by the various ports.